The present invention relates to a voltage detection circuit for detecting a power-supply voltage or the like, a power-on/off reset circuit, and a semiconductor device.
Recently, a technique has become popular for operating a semiconductor device in a stable condition in a wide power-supply voltage range by changing the internal circuit operation in accordance with the power-supply voltage value. For this reason, a voltage detection circuit for detecting a power-supply voltage value has become important.
A conventional voltage detection circuit will be explained hereinafter with reference to FIGS. 23-25. FIG. 23 shows the construction of the conventional voltage detection circuit. FIG. 24 shows the relationship between the power-supply voltage and the output voltage signal in the conventional voltage detection circuit. FIG. 25 shows the relationship between the power-supply voltage and the current drain.
Firstly, the circuit construction will be explained. As shown in FIG. 23, the Qp 61 is a P-channel type MOS transistor whose source is connected with the power-supply voltage VDD and whose gate and train are connected with the node N 61. The Qp 62 is a P-channel type MOS transistor whose source is connected with the node N 61 and whose gate and train are connected with the node N 62. The Qp 63 is a P-channel type MOS transistor whose source is connected with the node N 62 and whose gate and train are connected with the node N 63. The Qn 61 is an N-channel type MOS transistor whose source is connected with the ground voltage VSS, whose gate is connected with the power-supply voltage VDD, and whose train is connected with the node N 63. The Qp 64 is a P-channel type MOS transistor and the Qn 62 is an N-channel type MOS transistor which compose a first NOT circuit 61. The source, gate, and drain of the P-channel type MOS transistor Qp 64 are connected with the ground voltage VDD, the node N 63, and the node N 64, respectively. The source, gate, and drain of the N-channel type MOS transistor Qn 62 are connected with the ground voltage VSS, the node N 63, and the node N 64, respectively. The node N 64 is connected with the input terminal of a second NOT circuit 62. The second NOT circuit 62 is applied with the voltage detection signal VDT 60 from the node N 64, and generates the output voltage signal VOUT 60.
The operation of the voltage detection circuit will be explained as follows. As shown in FIG. 24, the logical voltage of the output voltage signal VOUT 60 which is obtained at the output terminal of the second NOT circuit 62 becomes xe2x80x9cLxe2x80x9d when the power-supply voltage VDD is less than 4V and becomes xe2x80x9cHxe2x80x9d when the voltage VDD is about 4V or higher under predetermined conditions.
This result is due to the following ground. The electric potential of the node N 63 is lower than the power-supply voltage VDD by the voltage drop of the P-channel type MOS transistors Qp 61-Qp 63. The electric potential becomes 2V, for example.
On the other hand, the threshold level of the first NOT circuit 61 which is composed of the P-channel type MOS transistor Qp 64 and the N-channel type MOS transistor Qn 62 is about xc2xd of the power-supply voltage VDD. Therefore, when the power-supply voltage VDD is about 4V, the electric potential of the node N 64 which is connected with the input terminal of the first NOT circuit 61 becomes about 2V, so that the logical voltage of the node N 64, or the voltage detection signal VDT goes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, and the logical voltage of the output voltage signal VOUT 60 which is the output of the second NOT circuit 62 goes from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d.
The current drain of the voltage detection circuit will be explained as follows. As shown in FIG. 24, when the power-supply voltage VDD is about 4V, the node N 63 which is the input terminal of the first NOT circuit 61 consisting of the P-channel type MOS transistor Qp 64 and the N-channel type MOS transistor Qn 62 has an intermediate electric potential between the power-supply voltage VDD and the ground voltage VSS. Consequently, both the P-channel type MOS transistor Qp 64 and the N-channel type MOS transistor Qn 62 are in the on state, that is, the first NOT circuit 61 temporarily falls into the short-circuit state. The current drain In 60 which runs through the N-channel type MOS transistor Qn 62 has a peak of 0.6 xcexcA or so. Even when the power-supply voltage VDD is not about 4V, the current drain In 60 is 0.1 xcexcA or higher as shown in FIG. 25.
However, in the conventional voltage detection circuit, when the electric potential of the node N 63 which is the input of the-first NOT circuit 61 has an intermediate electric potential between the power-supply voltage VDD and the ground voltage VSS, both the P-channel type MOS transistor Qp 64 and the N-channel type MOS transistor Qn 62 become the on state, that is, fall into temporary short-circuit state, which leads to an increase in the current drain. The current drain for the entire voltage detection circuit is large in other states, too.
In view of these problems, the object of the present invention is to provide a voltage detection circuit which reduces the peak of the current drain in the temporary short-circuit state and decreases the current drain as the entire circuit.
On the other hand, when a predetermined voltage is detected by the voltage detection circuit, a power-on/off reset circuit for immediately suspending the operations of the devices such as a logic circuit or a memory circuit might destroy memory data in the memory circuit when the operation is immediately suspended. Although there is no problem in the logic circuit, the memory circuit needs data re-writing (restore or refresh) after a readout. For this reason, it is difficult to properly terminate a sequence in operation.
In view of these problems, another object of the present invention is to provide a power-on/off reset circuit which properly terminates a sequence in operation.
The present invention includes the voltage detection circuit, power-on/off reset circuit, and semiconductor device which are constructed as follows.
The voltage detection circuit of the invention of claim 1 is characterized by comprising a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node.
The voltage detection circuit of the invention of claim 2 comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node and whose output terminal is a fourth node, a second NOT circuit whose input terminal is connected with the fourth node, whose output terminal is a fifth node, and which is connected between a third node and the ground voltage terminal, and a third MOS transistor whose gate is connected with the fifth node and which is connected between either the ground voltage terminal or the power-supply voltage terminal and the fourth node.
In the invention of claim 3, the first, second, and third MOS transistors of the invention of claim 2 are P-channel type MOS transistors, and the source of the third MOS transistor is connected with a power-supply voltage terminal.
The invention of claim 4 comprises a first voltage detection circuit which detects a first voltage and outputs a first signal, and a second voltage detection circuit which detects a second voltage lower than the first voltage and outputs a second signal, wherein the first voltage detection circuit comprises a first P-channel type MOS transistor whose gate and drain are connected with a first node, a second P-channel type MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage, a NOT circuit whose input terminal is the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a third MOS transistor which is connected between either the ground voltage terminal or a power-supply voltage terminal and the fourth node and whose gate is applied with the second signal of the second voltage detection circuit.
The invention of claim 5 is characterized in that in the invention of claim 4, the second signal which is outputted from the second voltage detection circuit is outputted only when the power supply is turned on.
The invention of claim 6 has a construction that in the invention of claim 4 the second signal which is outputted from the second voltage detection circuit is outputted for a certain time period after the power supply is turned on.
The voltage detection circuit of the invention of claim 7 comprises a first P-channel type MOS transistor whose gate and drain are connected with a first node, a second P-channel type MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, an N-channel type MOS transistor whose gate is connected with the second node, and a first NOT circuit whose input is the third node and whose output is a fourth node.
The invention of claim 8 has a construction that in the invention of claim 7 the first resistive element is an N-channel type MOS transistor.
The power-on/off reset circuit of the invention of claim 9 comprises a first voltage detection circuit which detects a first voltage and outputs a first signal, and prevents a new operational sequence when a power-supply voltage is equal to or lower than the first voltage.
The power-on/off reset circuit of the invention of claim 12 comprises a first voltage detection circuit which detects a first voltage and outputs a first signal, and a second voltage detection circuit which detects a second voltage lower than the first voltage and outputs a second signal, prevents a new operational sequence when a power-supply voltage is equal to or lower than the first voltage, and immediately suspends an operation when the power-supply voltage is equal to or lower than the second voltage.
The power-on/off reset circuit of the invention of claim 13 comprises a first voltage detection circuit which detects a first voltage and outputs a first signal, and a second voltage detection circuit which detects a second voltage lower than the first voltage and outputs a second signal, wherein a time for a power-supply voltage to drop from the first voltage to the second voltage is longer than a predetermined operational sequence completion time.
The voltage detection circuit of claim 14 comprises a first voltage detection circuit which (a) detects a first voltage and outputs a first signal, (b) outputs the first signal only when the power supply is turned on, and (c) outputs the first signal for a certain time period after the power supply is turned on, a second voltage detection circuit which detects a second voltage and outputs a second signal, a third voltage detection circuit which detects a third voltage higher than the second voltage, a fourth voltage detection circuit which detects a fourth voltage higher than the third voltage and outputs a fourth signal, a signal selection circuit which selects either the third signal or the fourth signal and outputs a fifth signal, a first control circuit which generates an OR output of the first signal and the second signal, and a second control circuit which generates an OR output of the first signal and the fifth signal.
The power-on/off reset circuit of claim 15 comprises a voltage detection circuit which detects a first voltage and a second voltage higher than the first voltage and outputs a first signal, wherein the first signal is transmitted at the second voltage when a power-supply voltage rises, and transmitted at the first voltage when the power-supply voltage drops, and a new operational sequence is prevented when the power-supply voltage is equal to or lower than the voltage for the first signal to be transmitted.
The power-on/off reset circuit of claim 16 comprises a first voltage detection circuit which detects a first voltage and a second voltage higher than the first voltage and outputs a first signal, and a second voltage detection circuit which detects a third voltage which is lower than the first voltage and outputs a second signal, wherein the first signal is transmitted at the second voltage when a power-supply voltage rises, and transmitted at the first voltage when the power-supply voltage drops, a new operational sequence is prevented when the power-supply voltage is equal to or lower than the voltage for the first signal to be transmitted, and an operation is immediately suspended when the power-supply voltage is equal to or lower than the third voltage.
The power-on/off reset circuit of claim 17 comprises a first voltage detection circuit which detects a first voltage and a second voltage higher than the first voltage, and outputs a first signal, and a second voltage detection circuit which detects a third voltage which is lower than the first voltage and outputs a second signal, wherein the first signal is transmitted at the second voltage when a power-supply voltage rises, and transmitted at the first voltage when the power-supply voltage drops, and a time for a power-supply voltage to drop from the first voltage to the third voltage is longer than a predetermined operational sequence completion time.
The semiconductor of the invention of claim 18 comprises the power-on/off reset circuit of claim 9 and a non-volatile memory, and the semiconductor does not operate the non-volatile memory when the power-supply voltage is equal to or lower than the first voltage of claim 9.
The semiconductor of the invention of claim 19 comprises the power-on/off reset circuit of claim 12 and a non-volatile memory, and the semiconductor does not operate the non-volatile memory when the power-supply voltage is equal to or lower than the second voltage of claim 12.
The semiconductor of the invention of claim 20 comprises the power-on/off reset circuit of claim 15 and a non-volatile memory, and the semiconductor does not operate the non-volatile memory when the power-supply voltage is equal to or lower than the voltage for the first signal of claim 15 to be transmitted or equal to or lower than the third voltage.
The semiconductor of the invention of claim 21 comprises the power-on/off reset circuit of claim 16 and a non-volatile memory, and the semiconductor does not operate the non-volatile memory when the power-supply voltage is equal to or lower than the voltage for the first signal of claim 12 to be transmitted or equal to or lower than the third voltage.
The inventions of claims 1-8 and 14 are voltage detection circuits which reduce the peak of the current drain and obtain a stable voltage detection signal. There is another effect that the stable voltage detection signal can be obtained even at a low voltage of turning on the power-supply.
The inventions of claims 9, 12, and 13 are power-on/off reset circuits which have an effect of not starting a new operational sequence mistakenly when the power supply is turned on, and properly terminating a sequence in operation when the power supply is turned off.
The inventions of claims 15, 16, and 17 have an effect of obtaining an operation stable against the fluctuation of the power-supply voltage by applying voltage hysteresis to the power-on/off reset voltage.
The inventions of claims 18, 19, 20, and 21 have an effect of obtaining an operation stable against the fluctuation of the power-supply voltage by applying voltage hysteresis to the power-on/off reset voltage, thereby preventing the wrong operation of the non-volatile memory which is under the control of this signal.